(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to define an opening in a stack of layers, to expose a fuse structure, located between rows of memory or logic cells.
(2) Description of Prior Art
As the density of cell designs, such as dynamic random access memory (DRAM), or static random access memory (SRAM), increase, rows or arrays of these specific cells are comprised with billions of discrete devices. However a single device failure, located in the high density cell, can result in an unusable memory chip. Therefore to allow the desired yield for chips comprised with high density cells to be realized, redundant, or additional rows of memory devices or cells, are formed on the chip, and then used if needed, to replace a defective row, thus resulting in a useable, high density chip. Rows of devices or cells, are physically connected to the main memory array via a fuse structure, which if broken can either delete a defective row, or add a redundant row, to the main array body. The fuse structure, comprised of a conductive material such as doped polysilicon or polycide (metal silicidexe2x80x94polysilicon), is usually formed from the same layer used to form the gate structure of the metal oxide semiconductor field effect transistor (MOSFET), discrete devices, used for the memory array cells. Therefore to access the fuse structure at the conclusion of device processing, for laser deleting, an opening (fuse opening), through many interlevel dielectric (ILD), layers, and intermetal dielectric (IMD) layers has to be defined.
The process for the fuse structure opening entails etching through many insulator layers, as well as etching through polysilicon layers, in the presence of a photoresist shape, used as an etch mask for definition of the fuse structure opening. Several problems have occurred during this complex etching procedure, one of which is the etching of a polysilicon layer used for interconnect and resistor purposes, covered by an inter-polysilicon oxide (IPO), layer, which in turn overlays the conductive fuse structure. The topography presented by the underlying conductive fuse structure, in combination with an anisotropic component of the fuse structure opening procedure, can result in unwanted polysilicon spacers on the sides of the IPO covered conductive plug structure. Additional over etching to remove the polysilicon spacers can damage the IPO layer overlying the defined fuse structure. This invention will describe a novel procedure for definition of the fuse structure opening, featuring isotropic removal of the polysilicon layer, performed in situ with the removal of the photoresist shape, used as an etch mask for definition of the fuse structure opening. Prior art, such as Huang et al, in U.S. Pat. No. 6,121,073, describe a method for creating a fuse structure opening, in a series of insulator layers, and in a polysilicon layer, however that prior art does not describe the novel in situ etching of a polysilicon layer, during the stripping procedure used to remove the photoresist shape used to define the fuse structure opening.
It is an object of this invention to form a fuse structure opening in stack of materials comprised of dielectric layers, and of a polysilicon layer, to expose an underlying conductive fuse structure.
It is another object of this invention to use an anisotropic dry etching procedure to form the fuse structure opening in the dielectric layers, while using a isotropic wet procedure to form the fuse structure opening in the polysilicon layer.
It is still another object of this invention to perform the isotropic wet etching component of the fuse structure opening procedure, used for etching of the polysilicon layer, in situ with the procedure used for removal of the fuse structure opening, photoresist shape.
In accordance with the present invention a method of forming a fuse structure opening, featuring a dry etching procedure for defining the fuse structure opening in dielectric layers, and an isotropic wet etch procedure for defining the fuse structure opening in a polysilicon layer, with the isotropic wet etch procedure performed in situ with the procedure used to remove the fuse structure opening, photoresist shape, is described. A photoresist shape, is formed on the top surface of a stack of materials comprising: dielectric layers; a polysilicon layer; an interlevel-poly oxide (IPO), layer; and a conductive fuse structure. A dry etching procedure is used to create a top portion of the fuse structure opening, in the dielectric layers, exposed in an opening in the photoresist shape, with the dry etching procedure terminating on the polysilicon layer. An isotropic wet etch procedure is next used to define the fuse structure opening in the polysilicon layer, with the isotropic wet etch procedure in situ removing the fuse structure opening, photoresist shape. The isotropic wet etching procedure results in exposure of the conductive structure, overlaid with the thin IPO layer.